A pure simulator for monadic concurrency with STM.
A pure simulator monad with support of concurrency (base & async style), stm, synchronous and asynchronous exceptions, timeouts & delays, dynamic traces, partial order reduction, and more. = Documentation Documentation is published [here](https://input-output-hk.github.io/io-sim/io-sim).
Alexander Vieth, Duncan Coutts, John Hughes, Marcin Szamotulski
Duncan Coutts duncan@well-typed.com, Marcin Szamotulski coot@coot.me
Apache-2.0
2026-03-24T08:52:16Z
r3: 2026-03-30T13:57:24Z
r2: 2026-03-28T08:51:44Z
r1: 2026-03-26T03:11:17Z